Jan, M. Rabaey, Anantha Chandrakasan and Borivoje Nikolić
Prentice Hall, 2003
Since the publication of the first edition of this book in 1996, CMOS manufacturing technology has continued its breathtaking pace, scaling to ever-smaller dimensions. Minimum feature sizes are now reaching the 100-nm realm. Circuits are becoming more complex, challenging the productivity of the designer, while the plunge into the deep-submicron space causes devices to behave differently and brings to the forefront a number of new issues that impact the reliability, cost, performance, power dissipation, and reliability of the digital IC. This updated text reflects the ongoing (r)evolution in the world of digital integrated circuit design, caused by this move into the deep-submicron realm. This means increased importance of deep- submicron transistor effects, interconnect, signal integrity, high-performance and low-power design, timing, and clock distribution. In contrast to the first edition, the present text focuses entirely on CMOS ICs.
Outstanding Features of the Text:
About the Cover: Detail of “Wet Orange,” by Joan Mitchell (American, 1925–1992). Oil on canvas, 112 ✕ 245 in. (284.5 ✕ 622.3 cm). Carnegie Museum of Art, Pittsburgh.
A complete slide set capturing the essence of the book is available for complimentary download. We only have one request: whenever using some of the slide material in your lectures, presentations or publications, please add the following acknowledgment: “Adopted from Digital Integrated Circuits, Rabaey, Chandrakasan and Nikolic, Prentice hall 2003.”
Videos of lectures based on the book and presented by Jan Rabaey at UC Berkeley in the Spring of 2012 can be found here (youtube)
Some material from the 1st edition did not make it into the 2nd. This is in particular the material concerned with non-CMOS digital design. For those interested, we have extracted the concerned sections and made them available in pdf-format.
